Automatic data movement and computation mapping for multi-level parallel architectures with explicitly managed memories.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/ppopp/BaskaranBKRRS08
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Automatic data movement and computation mapping for multi-level parallel architectures with explicitly managed memories.
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data movement, graphics processor unit, multi-level tiling, scratchpad memory
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Automatic data movement and computation mapping for multi-level parallel architectures with explicitly managed memories.
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