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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ppopp/BondhugulaRS07>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/J._Ramanujam>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/P._Sadayappan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Uday_Bondhugula>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1229428.1229446>
foaf:homepage <https://doi.org/10.1145/1229428.1229446>
dc:identifier DBLP conf/ppopp/BondhugulaRS07 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1229428.1229446 (xsd:string)
dcterms:issued 2007 (xsd:gYear)
rdfs:label Automatic mapping of nested loops to FPGAS. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/J._Ramanujam>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/P._Sadayappan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Uday_Bondhugula>
swrc:pages 101-111 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ppopp/2007>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ppopp/BondhugulaRS07/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ppopp/BondhugulaRS07>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ppopp/ppopp2007.html#BondhugulaRS07>
rdfs:seeAlso <https://doi.org/10.1145/1229428.1229446>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ppopp>
dc:subject FPGA, FPGA compilation, control signals, linear transformation, nested loops, regular processor arrays, resource constraints, scheduling (xsd:string)
dc:title Automatic mapping of nested loops to FPGAS. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document