A Single-Chip Fail-Safe Microprocessor with Memory Data Comparison Feature.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/prdc/ShimamuraTST06
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A Single-Chip Fail-Safe Microprocessor with Memory Data Comparison Feature.
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A Single-Chip Fail-Safe Microprocessor with Memory Data Comparison Feature.
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