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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/prdc/TsukisakaN00>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Masayuki_Tsukisaka>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Takashi_Nanya>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FPRDC.2000.897297>
foaf:homepage <https://doi.org/10.1109/PRDC.2000.897297>
dc:identifier DBLP conf/prdc/TsukisakaN00 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FPRDC.2000.897297 (xsd:string)
dcterms:issued 2000 (xsd:gYear)
rdfs:label A testable design for asynchronous fine-grain pipeline circuits. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Masayuki_Tsukisaka>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Takashi_Nanya>
swrc:pages 148-155 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/prdc/2000>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/prdc/TsukisakaN00/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/prdc/TsukisakaN00>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/prdc/prdc2000.html#TsukisakaN00>
rdfs:seeAlso <https://doi.org/10.1109/PRDC.2000.897297>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/prdc>
dc:subject logic testing; logic CAD; SPICE; testable design; asynchronous fine-grain pipeline circuits; dynamic gates; high-performance datapath design; pipeline latches; scan path; scan latch libraries; SPICE simulation; CMOS technology (xsd:string)
dc:title A testable design for asynchronous fine-grain pipeline circuits. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document