A testable design for asynchronous fine-grain pipeline circuits.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/prdc/TsukisakaN00
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A testable design for asynchronous fine-grain pipeline circuits.
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logic testing; logic CAD; SPICE; testable design; asynchronous fine-grain pipeline circuits; dynamic gates; high-performance datapath design; pipeline latches; scan path; scan latch libraries; SPICE simulation; CMOS technology
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A testable design for asynchronous fine-grain pipeline circuits.
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