[RDF data]
Home | Example Publications
PropertyValue
dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/prime/BelliziaPST18>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Alessandro_Trifiletti>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Davide_Bellizia>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Gaetano_Palumbo>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Giuseppe_Scotti>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FPRIME.2018.8430320>
foaf:homepage <https://doi.org/10.1109/PRIME.2018.8430320>
dc:identifier DBLP conf/prime/BelliziaPST18 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FPRIME.2018.8430320 (xsd:string)
dcterms:issued 2018 (xsd:gYear)
rdfs:label A Novel Very Low Voltage Topology to implement MCML XOR Gates. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Alessandro_Trifiletti>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Davide_Bellizia>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Gaetano_Palumbo>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Giuseppe_Scotti>
swrc:pages 157-160 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/prime/2018>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/prime/BelliziaPST18/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/prime/BelliziaPST18>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/prime/prime2018.html#BelliziaPST18>
rdfs:seeAlso <https://doi.org/10.1109/PRIME.2018.8430320>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/prime>
dc:title A Novel Very Low Voltage Topology to implement MCML XOR Gates. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document