Memory-Efficiency and High-Speed Architectures for Forward and Inverse DCT with Multiplierless Operation.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/psivt/SungSSH06
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Memory-Efficiency and High-Speed Architectures for Forward and Inverse DCT with Multiplierless Operation.
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DCT, IDCT, parallel-pipelined architecture, memory-efficiency, high-performances.
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Memory-Efficiency and High-Speed Architectures for Forward and Inverse DCT with Multiplierless Operation.
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