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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/rcar/PengLLLZF16>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Congyi_Lyu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jianqing_Peng>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kun_Fan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Weiguo_Zhou>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yunhui_Li>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yunhui_Liu>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FRCAR.2016.7784039>
foaf:homepage <https://doi.org/10.1109/RCAR.2016.7784039>
dc:identifier DBLP conf/rcar/PengLLLZF16 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FRCAR.2016.7784039 (xsd:string)
dcterms:issued 2016 (xsd:gYear)
rdfs:label FPGA-based parallel hardware architecture for SIFT algorithm. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Congyi_Lyu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jianqing_Peng>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kun_Fan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Weiguo_Zhou>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yunhui_Li>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yunhui_Liu>
swrc:pages 277-282 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/rcar/2016>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/rcar/PengLLLZF16/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/rcar/PengLLLZF16>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/rcar/rcar2016.html#PengLLLZF16>
rdfs:seeAlso <https://doi.org/10.1109/RCAR.2016.7784039>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/rcar>
dc:title FPGA-based parallel hardware architecture for SIFT algorithm. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document