Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/reconfig/AmouriMMM09
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Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing.
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MFPGA, Placement, Routing, Timing balance, Differential Power Analysis, WDDL
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Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing.
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