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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/reconfig/CooleWS09>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Greg_Stitt>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/James_Coole>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/John_Robert_Wernsing>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FReConFig.2009.68>
foaf:homepage <https://doi.org/10.1109/ReConFig.2009.68>
dc:identifier DBLP conf/reconfig/CooleWS09 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FReConFig.2009.68 (xsd:string)
dcterms:issued 2009 (xsd:gYear)
rdfs:label A Traversal Cache Framework for FPGA Acceleration of Pointer Data Structures: A Case Study on Barnes-Hut N-body Simulation. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Greg_Stitt>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/James_Coole>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/John_Robert_Wernsing>
swrc:pages 143-148 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/reconfig/2009>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/reconfig/CooleWS09/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/reconfig/CooleWS09>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/reconfig/reconfig2009.html#CooleWS09>
rdfs:seeAlso <https://doi.org/10.1109/ReConFig.2009.68>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/reconfig>
dc:subject FPGA, traversal cache, pointers, speedup (xsd:string)
dc:title A Traversal Cache Framework for FPGA Acceleration of Pointer Data Structures: A Case Study on Barnes-Hut N-body Simulation. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document