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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/reconfig/DegryseBDS08>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Dirk_Stroobandt>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Harald_Devos>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Karel_Bruneel>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tom_Degryse>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FReConFig.2008.25>
foaf:homepage <https://doi.org/10.1109/ReConFig.2008.25>
dc:identifier DBLP conf/reconfig/DegryseBDS08 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FReConFig.2008.25 (xsd:string)
dcterms:issued 2008 (xsd:gYear)
rdfs:label Loop Transformations to Reduce the Dynamic FPGA Recon?guration Overhead. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Dirk_Stroobandt>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Harald_Devos>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Karel_Bruneel>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tom_Degryse>
swrc:pages 133-138 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/reconfig/2008>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/reconfig/DegryseBDS08/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/reconfig/DegryseBDS08>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/reconfig/reconfig2008.html#DegryseBDS08>
rdfs:seeAlso <https://doi.org/10.1109/ReConFig.2008.25>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/reconfig>
dc:subject FPGAs, Loop transformations, Dynamic hardware generation, Matrix multiplications (xsd:string)
dc:title Loop Transformations to Reduce the Dynamic FPGA Recon?guration Overhead. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document