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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/reconfig/NoronhaPW17>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Daniel_H._Noronha>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jose_P._Pinilla>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Steven_J._E._Wilton>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FRECONFIG.2017.8279807>
foaf:homepage <https://doi.org/10.1109/RECONFIG.2017.8279807>
dc:identifier DBLP conf/reconfig/NoronhaPW17 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FRECONFIG.2017.8279807 (xsd:string)
dcterms:issued 2017 (xsd:gYear)
rdfs:label Rapid circuit-specific inlining tuning for FPGA high-level synthesis. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Daniel_H._Noronha>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jose_P._Pinilla>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Steven_J._E._Wilton>
swrc:pages 1-6 (xsd:string)
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rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/reconfig/reconfig2017.html#NoronhaPW17>
rdfs:seeAlso <https://doi.org/10.1109/RECONFIG.2017.8279807>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/reconfig>
dc:title Rapid circuit-specific inlining tuning for FPGA high-level synthesis. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document