Decimal Adders/Subtractors in FPGA: Efficient 6-input LUT Implementations.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/reconfig/VazquezSBD09
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Decimal Adders/Subtractors in FPGA: Efficient 6-input LUT Implementations.
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Decimal Adders/Subtractors in FPGA: Efficient 6-input LUT Implementations.
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