A single-FPGA architecture for detecting heavy hitters in 100 Gbit/s ethernet links.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/reconfig/ZazoLRS17
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A single-FPGA architecture for detecting heavy hitters in 100 Gbit/s ethernet links.
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A single-FPGA architecture for detecting heavy hitters in 100 Gbit/s ethernet links.
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