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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/recosoc/JosephBWEGP17>
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dc:creator <https://dblp.l3s.de/d2r/resource/authors/Dominik_Ermel>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jan_Moritz_Joseph>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Lennart_Bamberg>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sven_Wrieden>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Thilo_Pionteck>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FReCoSoC.2017.8016143>
foaf:homepage <https://doi.org/10.1109/ReCoSoC.2017.8016143>
dc:identifier DBLP conf/recosoc/JosephBWEGP17 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FReCoSoC.2017.8016143 (xsd:string)
dcterms:issued 2017 (xsd:gYear)
rdfs:label Design method for asymmetric 3D interconnect architectures with high level models. (xsd:string)
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foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Lennart_Bamberg>
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foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Thilo_Pionteck>
swrc:pages 1-8 (xsd:string)
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rdfs:seeAlso <https://doi.org/10.1109/ReCoSoC.2017.8016143>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/recosoc>
dc:title Design method for asymmetric 3D interconnect architectures with high level models. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document