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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/recosoc/RodriguezVCPTR15>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Alfonso_Rodr%E2%88%9A%E2%89%A0guez_0002>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Cesar_Castanares>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Eduardo_de_la_Torre>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jorge_Portilla>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Juan_Valverde>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Teresa_Riesgo>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FReCoSoC.2015.7238086>
foaf:homepage <https://doi.org/10.1109/ReCoSoC.2015.7238086>
dc:identifier DBLP conf/recosoc/RodriguezVCPTR15 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FReCoSoC.2015.7238086 (xsd:string)
dcterms:issued 2015 (xsd:gYear)
rdfs:label Execution modeling in self-aware FPGA-based architectures for efficient resource management. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Alfonso_Rodr%E2%88%9A%E2%89%A0guez_0002>
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foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Eduardo_de_la_Torre>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jorge_Portilla>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Juan_Valverde>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Teresa_Riesgo>
swrc:pages 1-8 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/recosoc/2015>
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rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/recosoc/recosoc2015.html#RodriguezVCPTR15>
rdfs:seeAlso <https://doi.org/10.1109/ReCoSoC.2015.7238086>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/recosoc>
dc:title Execution modeling in self-aware FPGA-based architectures for efficient resource management. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document