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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/rev/CristeaB22>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Alexandra_Balan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Andreea_Cristina_Suiu_Cristea>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F978-3-031-17091-1%5F5>
foaf:homepage <https://doi.org/10.1007/978-3-031-17091-1_5>
dc:identifier DBLP conf/rev/CristeaB22 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F978-3-031-17091-1%5F5 (xsd:string)
dcterms:issued 2022 (xsd:gYear)
rdfs:label AES Hardware Implementation Based on FPGA with Improved Throughput. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Alexandra_Balan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Andreea_Cristina_Suiu_Cristea>
swrc:pages 41-50 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/rev/2022>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/rev/CristeaB22/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/rev/CristeaB22>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/rev/rev2022.html#CristeaB22>
rdfs:seeAlso <https://doi.org/10.1007/978-3-031-17091-1_5>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/rev>
dc:title AES Hardware Implementation Based on FPGA with Improved Throughput. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document