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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/rsp/ChattopadhyaySZLAM06>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Anupam_Chattopadhyay>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Arnab_Sinha>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Diandian_Zhang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Gerd_Ascheid>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Heinrich_Meyr>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rainer_Leupers>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FRSP.2006.21>
foaf:homepage <https://doi.org/10.1109/RSP.2006.21>
dc:identifier DBLP conf/rsp/ChattopadhyaySZLAM06 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FRSP.2006.21 (xsd:string)
dcterms:issued 2006 (xsd:gYear)
rdfs:label Integrated Verification Approach during ADL-Driven Processor Design. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Anupam_Chattopadhyay>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Arnab_Sinha>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Diandian_Zhang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Gerd_Ascheid>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Heinrich_Meyr>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rainer_Leupers>
swrc:pages 110-118 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/rsp/2006>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/rsp/ChattopadhyaySZLAM06/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/rsp/ChattopadhyaySZLAM06>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/rsp/rsp2006.html#ChattopadhyaySZLAM06>
rdfs:seeAlso <https://doi.org/10.1109/RSP.2006.21>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/rsp>
dc:title Integrated Verification Approach during ADL-Driven Processor Design. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document