| Property | Value |
|---|
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dcterms:bibliographicCitation
|
<http://dblp.uni-trier.de/rec/bibtex/conf/rsp/HeathT01>
|
|
dc:creator
|
<https://dblp.l3s.de/d2r/resource/authors/Andrew_Tan>
|
|
dc:creator
|
<https://dblp.l3s.de/d2r/resource/authors/J._Robert_Heath>
|
|
foaf:homepage
|
<http://dx.doi.org/doi.org%2F10.1109%2FIWRSP.2001.933850>
|
|
foaf:homepage
|
<https://doi.org/10.1109/IWRSP.2001.933850>
|
|
dc:identifier
|
DBLP conf/rsp/HeathT01
(xsd:string)
|
|
dc:identifier
|
DOI doi.org%2F10.1109%2FIWRSP.2001.933850
(xsd:string)
|
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dcterms:issued
|
2001
(xsd:gYear)
|
|
rdfs:label
|
Modeling, Design, Virtual and Physical Prototyping, Testing, and Verification of a Multifunctional Processor Queue for a Single-Chip Multiprocessor Architecture.
(xsd:string)
|
|
foaf:maker
|
<https://dblp.l3s.de/d2r/resource/authors/Andrew_Tan>
|
|
foaf:maker
|
<https://dblp.l3s.de/d2r/resource/authors/J._Robert_Heath>
|
|
swrc:pages
|
128-135
(xsd:string)
|
|
dcterms:partOf
|
<https://dblp.l3s.de/d2r/resource/publications/conf/rsp/2001>
|
|
owl:sameAs
|
<http://bibsonomy.org/uri/bibtexkey/conf/rsp/HeathT01/dblp>
|
|
owl:sameAs
|
<http://dblp.rkbexplorer.com/id/conf/rsp/HeathT01>
|
|
rdfs:seeAlso
|
<http://dblp.uni-trier.de/db/conf/rsp/rsp2001.html#HeathT01>
|
|
rdfs:seeAlso
|
<https://doi.org/10.1109/IWRSP.2001.933850>
|
|
swrc:series
|
<https://dblp.l3s.de/d2r/resource/conferences/rsp>
|
|
dc:subject
|
Real-time reconfigurable architecture, analytic functional modeling, design, FPGA prototyping, real-time testing, and functional/performance verification.
(xsd:string)
|
|
dc:title
|
Modeling, Design, Virtual and Physical Prototyping, Testing, and Verification of a Multifunctional Processor Queue for a Single-Chip Multiprocessor Architecture.
(xsd:string)
|
|
dc:type
|
<http://purl.org/dc/dcmitype/Text>
|
|
rdf:type
|
swrc:InProceedings
|
|
rdf:type
|
foaf:Document
|
![[RDF data]](https://dblp.l3s.de/d2r/snorql/rdf_flyer.24.gif)