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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/rsp/SeeleySDPK17>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kenneth_B._Kent>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Panagiotis_Patros>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sean_Seeley>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Vidya_Sankaranaryanan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zack_Deveau>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F3130265.3130326>
foaf:homepage <https://doi.org/10.1145/3130265.3130326>
dc:identifier DBLP conf/rsp/SeeleySDPK17 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F3130265.3130326 (xsd:string)
dcterms:issued 2017 (xsd:gYear)
rdfs:label Simulation-based circuit-activity estimation for FPGAs containing hard blocks. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kenneth_B._Kent>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Panagiotis_Patros>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sean_Seeley>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Vidya_Sankaranaryanan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zack_Deveau>
swrc:pages 36-42 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/rsp/2017>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/rsp/SeeleySDPK17/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/rsp/SeeleySDPK17>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/rsp/rsp2017.html#SeeleySDPK17>
rdfs:seeAlso <https://doi.org/10.1145/3130265.3130326>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/rsp>
dc:title Simulation-based circuit-activity estimation for FPGAs containing hard blocks. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document