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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/rtss/LiMW96>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Andrew_Wolfe>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sharad_Malik>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yau-Tsun_Steven_Li>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FREAL.1996.563722>
foaf:homepage <https://doi.org/10.1109/REAL.1996.563722>
dc:identifier DBLP conf/rtss/LiMW96 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FREAL.1996.563722 (xsd:string)
dcterms:issued 1996 (xsd:gYear)
rdfs:label Cache modeling for real-time software: beyond direct mapped instruction caches. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Andrew_Wolfe>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sharad_Malik>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yau-Tsun_Steven_Li>
swrc:pages 254-263 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/rtss/1996>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/rtss/LiMW96/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/rtss/LiMW96>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/rtss/rtss1996.html#LiMW96>
rdfs:seeAlso <https://doi.org/10.1109/REAL.1996.563722>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/rtss>
dc:subject cache storage; cache modeling; real-time software; direct mapped instruction caches; tight bound; worst case execution time; hardware system; memory performance; worst case timing analysis; cache hits; cache misses; integer-linear-programming; set associative instruction caches; data caches; unified caches; research; design tool; cinderella (xsd:string)
dc:title Cache modeling for real-time software: beyond direct mapped instruction caches. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document