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dc:creator <https://dblp.l3s.de/d2r/resource/authors/S%E2%88%9A%C2%B0ndor-Tiham%E2%88%9A%C2%A9r_Brassai>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/S._Dan>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FSACI.2007.375494>
foaf:homepage <https://doi.org/10.1109/SACI.2007.375494>
dc:identifier DBLP conf/saci/BrassaiBD07 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FSACI.2007.375494 (xsd:string)
dcterms:issued 2007 (xsd:gYear)
rdfs:label FPGA Parallel Implementation of CMAC Type Neural Network with on Chip Learning. (xsd:string)
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foaf:maker <https://dblp.l3s.de/d2r/resource/authors/S._Dan>
swrc:pages 111-115 (xsd:string)
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rdfs:seeAlso <https://doi.org/10.1109/SACI.2007.375494>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/saci>
dc:title FPGA Parallel Implementation of CMAC Type Neural Network with on Chip Learning. (xsd:string)
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rdf:type swrc:InProceedings
rdf:type foaf:Document