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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/samos/BerekovicN06>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mladen_Berekovic>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tim_Niggemeier>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F11796435%5F30>
foaf:homepage <https://doi.org/10.1007/11796435_30>
dc:identifier DBLP conf/samos/BerekovicN06 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F11796435%5F30 (xsd:string)
dcterms:issued 2006 (xsd:gYear)
rdfs:label A Scalable, Multi-thread, Multi-issue Array Processor Architecture for DSP Applications Based on Extended Tomasulo Scheme. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mladen_Berekovic>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tim_Niggemeier>
swrc:pages 289-298 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/samos/2006>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/samos/BerekovicN06/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/samos/BerekovicN06>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/samos/samos2006.html#BerekovicN06>
rdfs:seeAlso <https://doi.org/10.1007/11796435_30>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/samos>
dc:title A Scalable, Multi-thread, Multi-issue Array Processor Architecture for DSP Applications Based on Extended Tomasulo Scheme. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document