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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/sasp/VenugopalHL11>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Daniel_L._Lau>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/J._Robert_Heath>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rishvanth_Kora_Venugopal>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FSASP.2011.5941080>
foaf:homepage <https://doi.org/10.1109/SASP.2011.5941080>
dc:identifier DBLP conf/sasp/VenugopalHL11 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FSASP.2011.5941080 (xsd:string)
dcterms:issued 2011 (xsd:gYear)
rdfs:label FPGA based parallel architecture implementation of Stacked Error Diffusion algorithm. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Daniel_L._Lau>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/J._Robert_Heath>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rishvanth_Kora_Venugopal>
swrc:pages 66-69 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/sasp/2011>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/sasp/VenugopalHL11/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/sasp/VenugopalHL11>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/sasp/sasp2011.html#VenugopalHL11>
rdfs:seeAlso <https://doi.org/10.1109/SASP.2011.5941080>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/sasp>
dc:title FPGA based parallel architecture implementation of Stacked Error Diffusion algorithm. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document