ASIC design of a novel high performance neuroprocessor architecture for multi layered perceptron networks.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/sbcci/MirandaC09
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ASIC design of a novel high performance neuroprocessor architecture for multi layered perceptron networks.
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ASIC, neural network arithmetic, neuroprocessor
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ASIC design of a novel high performance neuroprocessor architecture for multi layered perceptron networks.
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