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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/sbcci/RosaRRMS07>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Andr%E2%88%9A%C2%A9_In%E2%88%9A%C2%B0cio_Reis>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Felipe_Ribeiro_Schneider>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Felipe_de_Souza_Marques>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Leomar_S._da_Rosa_Jr.>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Renato_P._Ribas>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1284480.1284511>
foaf:homepage <https://doi.org/10.1145/1284480.1284511>
dc:identifier DBLP conf/sbcci/RosaRRMS07 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1284480.1284511 (xsd:string)
dcterms:issued 2007 (xsd:gYear)
rdfs:label A comparative study of CMOS gates with minimum transistor stacks. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Andr%E2%88%9A%C2%A9_In%E2%88%9A%C2%B0cio_Reis>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Felipe_Ribeiro_Schneider>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Felipe_de_Souza_Marques>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Leomar_S._da_Rosa_Jr.>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Renato_P._Ribas>
swrc:pages 93-98 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/sbcci/2007>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/sbcci/RosaRRMS07/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/sbcci/RosaRRMS07>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/sbcci/sbcci2007.html#RosaRRMS07>
rdfs:seeAlso <https://doi.org/10.1145/1284480.1284511>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/sbcci>
dc:subject BDDs, CMOS gates, PTL, logical effort, switch theory, technology mapping, unateness (xsd:string)
dc:title A comparative study of CMOS gates with minimum transistor stacks. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document