A methodology for tuning two-level cache hierarchy considering energy and performance.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/sbcci/Silva-FilhoA09
Home
|
Example Publications
Property
Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/sbcci/Silva-FilhoA09
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Abel_G._Silva-Filho
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Cristiano_C._de_Ara%E2%88%9A%C4%BCjo
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1145%2F1601896.1601905
>
foaf:
homepage
<
https://doi.org/10.1145/1601896.1601905
>
dc:
identifier
DBLP conf/sbcci/Silva-FilhoA09
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1145%2F1601896.1601905
(xsd:string)
dcterms:
issued
2009
(xsd:gYear)
rdfs:
label
A methodology for tuning two-level cache hierarchy considering energy and performance.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Abel_G._Silva-Filho
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Cristiano_C._de_Ara%E2%88%9A%C4%BCjo
>
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/sbcci/2009
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/sbcci/Silva-FilhoA09/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/sbcci/Silva-FilhoA09
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/sbcci/sbcci2009.html#Silva-FilhoA09
>
rdfs:
seeAlso
<
https://doi.org/10.1145/1601896.1601905
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/sbcci
>
dc:
subject
embedded systems, exploration mechanism, low power design, memory hierarchy, system-on-chip, two-level caches
(xsd:string)
dc:
title
A methodology for tuning two-level cache hierarchy considering energy and performance.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document