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dc:creator <https://dblp.l3s.de/d2r/resource/authors/M%E2%88%9A%C2%B0rio_P._V%E2%88%9A%C2%A9stias>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1150343.1150365>
foaf:homepage <https://doi.org/10.1145/1150343.1150365>
dc:identifier DBLP conf/sbcci/VestiasN06 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1150343.1150365 (xsd:string)
dcterms:issued 2006 (xsd:gYear)
rdfs:label Area and performance optimization of a generic network-on-chip architecture. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hor%E2%88%9A%C2%B0cio_C._Neto>
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swrc:pages 68-73 (xsd:string)
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rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/sbcci/sbcci2006.html#VestiasN06>
rdfs:seeAlso <https://doi.org/10.1145/1150343.1150365>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/sbcci>
dc:subject FPGA, network-on-chip, system-on-chip (xsd:string)
dc:title Area and performance optimization of a generic network-on-chip architecture. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document