Area and performance optimization of a generic network-on-chip architecture.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/sbcci/VestiasN06
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2006
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Area and performance optimization of a generic network-on-chip architecture.
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FPGA, network-on-chip, system-on-chip
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Area and performance optimization of a generic network-on-chip architecture.
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