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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/sc/LaukemannHHHW18>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Georg_Hager>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Gerhard_Wellein>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jan_Laukemann>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Johannes_Hofmann_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Julian_Hammer>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FPMBS.2018.8641578>
foaf:homepage <https://doi.org/10.1109/PMBS.2018.8641578>
dc:identifier DBLP conf/sc/LaukemannHHHW18 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FPMBS.2018.8641578 (xsd:string)
dcterms:issued 2018 (xsd:gYear)
rdfs:label Automated Instruction Stream Throughput Prediction for Intel and AMD Microarchitectures. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Georg_Hager>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Gerhard_Wellein>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jan_Laukemann>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Johannes_Hofmann_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Julian_Hammer>
swrc:pages 121-131 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/sc/2018pmbs>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/sc/LaukemannHHHW18/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/sc/LaukemannHHHW18>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/sc/pmbs2018.html#LaukemannHHHW18>
rdfs:seeAlso <https://doi.org/10.1109/PMBS.2018.8641578>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/sc>
dc:title Automated Instruction Stream Throughput Prediction for Intel and AMD Microarchitectures. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document