Designing Combinational Circuits with List Homomorphisms. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

Property	Value
dcterms:bibliographicCitation	<http://dblp.uni-trier.de/rec/bibtex/conf/sera/Dosch05>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Walter_Dosch>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FSERA.2005.35>
foaf:homepage	<https://doi.org/10.1109/SERA.2005.35>
dc:identifier	DBLP conf/sera/Dosch05 (xsd:string)
dc:identifier	DOI doi.org%2F10.1109%2FSERA.2005.35 (xsd:string)
dcterms:issued	2005 (xsd:gYear)
rdfs:label	Designing Combinational Circuits with List Homomorphisms. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Walter_Dosch>
swrc:pages	288-297 (xsd:string)
dcterms:partOf	<https://dblp.l3s.de/d2r/resource/publications/conf/sera/2005>
owl:sameAs	<http://bibsonomy.org/uri/bibtexkey/conf/sera/Dosch05/dblp>
owl:sameAs	<http://dblp.rkbexplorer.com/id/conf/sera/Dosch05>
rdfs:seeAlso	<http://dblp.uni-trier.de/db/conf/sera/sera2005.html#Dosch05>
rdfs:seeAlso	<https://doi.org/10.1109/SERA.2005.35>
swrc:series	<https://dblp.l3s.de/d2r/resource/conferences/sera>
dc:subject	High-level synthesis, functional hardware description, list homomorphism, tree network, iterative network, parity generator, comparator, priority resolution (xsd:string)
dc:title	Designing Combinational Circuits with List Homomorphisms. (xsd:string)
dc:type	<http://purl.org/dc/dcmitype/Text>
rdf:type	swrc:InProceedings
rdf:type	foaf:Document