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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/sigmod/Dann0F21>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Daniel_Ritter_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Holger_Fr%E2%88%9A%E2%88%82ning>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jonas_Dann>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F3461837.3464512>
foaf:homepage <https://doi.org/10.1145/3461837.3464512>
dc:identifier DBLP conf/sigmod/Dann0F21 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F3461837.3464512 (xsd:string)
dcterms:issued 2021 (xsd:gYear)
rdfs:label Demystifying memory access patterns of FPGA-based graph processing accelerators. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Daniel_Ritter_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Holger_Fr%E2%88%9A%E2%88%82ning>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jonas_Dann>
swrc:pages 3:1-3:10 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/sigmod/2021grades>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/sigmod/Dann0F21/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/sigmod/Dann0F21>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/sigmod/grades2021.html#Dann0F21>
rdfs:seeAlso <https://doi.org/10.1145/3461837.3464512>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/sigmod>
dc:title Demystifying memory access patterns of FPGA-based graph processing accelerators. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document