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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/sii/TranTH24>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Lien-Bach_Tran>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Thi-Uyen_Ha>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Van-Tien_Tran>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FSII58957.2024.10417699>
foaf:homepage <https://doi.org/10.1109/SII58957.2024.10417699>
dc:identifier DBLP conf/sii/TranTH24 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FSII58957.2024.10417699 (xsd:string)
dcterms:issued 2024 (xsd:gYear)
rdfs:label A 0.392ms FPGA-Based Channel Estimation Design Implementing Fine Symbol Timing Offset and Residual Carrier Frequency Offset Cancellation for 2√ó4 MIMO Uplink in 5G Microcells. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Lien-Bach_Tran>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Thi-Uyen_Ha>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Van-Tien_Tran>
swrc:pages 1158-1163 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/sii/2024>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/sii/TranTH24/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/sii/TranTH24>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/sii/sii2024.html#TranTH24>
rdfs:seeAlso <https://doi.org/10.1109/SII58957.2024.10417699>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/sii>
dc:title A 0.392ms FPGA-Based Channel Estimation Design Implementing Fine Symbol Timing Offset and Residual Carrier Frequency Offset Cancellation for 2√ó4 MIMO Uplink in 5G Microcells. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document