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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/sips/LinSWZC07>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jun-Jie_Zhu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kuang-Hui_Wang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ming-Hwa_Sheu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Si-Ying_Chen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Su-Hon_Lin>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FSIPS.2007.4387534>
foaf:homepage <https://doi.org/10.1109/SIPS.2007.4387534>
dc:identifier DBLP conf/sips/LinSWZC07 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FSIPS.2007.4387534 (xsd:string)
dcterms:issued 2007 (xsd:gYear)
rdfs:label Efficient VLSI Design of Modulo 2n-1 Adder Using Hybrid Carry Selection. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jun-Jie_Zhu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kuang-Hui_Wang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ming-Hwa_Sheu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Si-Ying_Chen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Su-Hon_Lin>
swrc:pages 142-145 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/sips/2007>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/sips/LinSWZC07/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/sips/LinSWZC07>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/sips/sips2007.html#LinSWZC07>
rdfs:seeAlso <https://doi.org/10.1109/SIPS.2007.4387534>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/sips>
dc:title Efficient VLSI Design of Modulo 2n-1 Adder Using Hybrid Carry Selection. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document