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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/sips/YuLMW21>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jiapeng_Luo>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wendong_Mao>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yue_Yu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zhongfeng_Wang_0001>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FSiPS52927.2021.00033>
foaf:homepage <https://doi.org/10.1109/SiPS52927.2021.00033>
dc:identifier DBLP conf/sips/YuLMW21 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FSiPS52927.2021.00033 (xsd:string)
dcterms:issued 2021 (xsd:gYear)
rdfs:label A Memory-Efficient Hardware Architecture for Deformable Convolutional Networks. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jiapeng_Luo>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wendong_Mao>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yue_Yu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zhongfeng_Wang_0001>
swrc:pages 140-145 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/sips/2021>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/sips/YuLMW21/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/sips/YuLMW21>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/sips/sips2021.html#YuLMW21>
rdfs:seeAlso <https://doi.org/10.1109/SiPS52927.2021.00033>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/sips>
dc:title A Memory-Efficient Hardware Architecture for Deformable Convolutional Networks. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document