Floorplan-based FPGA interconnect power estimation in DSP circuits.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/slip/JevticCP09
Home
|
Example Publications
Property
Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/slip/JevticCP09
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Carlos_Carreras
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Ruzica_Jevtic
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Vukasin_Pejovic
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1145%2F1572471.1572481
>
foaf:
homepage
<
https://doi.org/10.1145/1572471.1572481
>
dc:
identifier
DBLP conf/slip/JevticCP09
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1145%2F1572471.1572481
(xsd:string)
dcterms:
issued
2009
(xsd:gYear)
rdfs:
label
Floorplan-based FPGA interconnect power estimation in DSP circuits.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Carlos_Carreras
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Ruzica_Jevtic
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Vukasin_Pejovic
>
swrc:
pages
53-60
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/slip/2009
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/slip/JevticCP09/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/slip/JevticCP09
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/slip/slip2009.html#JevticCP09
>
rdfs:
seeAlso
<
https://doi.org/10.1145/1572471.1572481
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/slip
>
dc:
subject
fpga, interconnects, low power, power estimation
(xsd:string)
dc:
title
Floorplan-based FPGA interconnect power estimation in DSP circuits.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document