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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/slip/MorgenshteinFGK08>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Arkadiy_Morgenshtein>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Avinoam_Kolodny>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Eby_G._Friedman>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ran_Ginosar>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1353610.1353615>
foaf:homepage <https://doi.org/10.1145/1353610.1353615>
dc:identifier DBLP conf/slip/MorgenshteinFGK08 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1353610.1353615 (xsd:string)
dcterms:issued 2008 (xsd:gYear)
rdfs:label Timing optimization in logic with interconnect. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Arkadiy_Morgenshtein>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Avinoam_Kolodny>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Eby_G._Friedman>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ran_Ginosar>
swrc:pages 19-26 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/slip/2008>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/slip/MorgenshteinFGK08/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/slip/MorgenshteinFGK08>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/slip/slip2008.html#MorgenshteinFGK08>
rdfs:seeAlso <https://doi.org/10.1145/1353610.1353615>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/slip>
dc:subject interconnect, logic circuits, logical effort, repeaters, timing optimization (xsd:string)
dc:title Timing optimization in logic with interconnect. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document