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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/slip/ZhangYHAEC09>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/A._Ege_Engin>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Amirali_Shayan_Arani>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chung-Kuan_Cheng>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wanping_Zhang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wenjian_Yu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xiang_Hu>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1572471.1572487>
foaf:homepage <https://doi.org/10.1145/1572471.1572487>
dc:identifier DBLP conf/slip/ZhangYHAEC09 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1572471.1572487 (xsd:string)
dcterms:issued 2009 (xsd:gYear)
rdfs:label Predicting the worst-case voltage violation in a 3D power network. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/A._Ege_Engin>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Amirali_Shayan_Arani>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chung-Kuan_Cheng>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wanping_Zhang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wenjian_Yu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xiang_Hu>
swrc:pages 93-98 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/slip/2009>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/slip/ZhangYHAEC09/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/slip/ZhangYHAEC09>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/slip/slip2009.html#ZhangYHAEC09>
rdfs:seeAlso <https://doi.org/10.1145/1572471.1572487>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/slip>
dc:subject clock gating, integer linear programming, leakage, power networks, worst case violation prediction (xsd:string)
dc:title Predicting the worst-case voltage violation in a 3D power network. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document