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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/smacd/YasinSPC23>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Atif_Yasin>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Maciej_J._Ciesielski>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/S%E2%88%9A%C2%A9bastien_Pillement>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tiankai_Su>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FSMACD58065.2023.10192137>
foaf:homepage <https://doi.org/10.1109/SMACD58065.2023.10192137>
dc:identifier DBLP conf/smacd/YasinSPC23 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FSMACD58065.2023.10192137 (xsd:string)
dcterms:issued 2023 (xsd:gYear)
rdfs:label Formal Verification of Divider Circuits by Hardware Reduction. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Atif_Yasin>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Maciej_J._Ciesielski>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/S%E2%88%9A%C2%A9bastien_Pillement>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tiankai_Su>
swrc:pages 1-4 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/smacd/2023>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/smacd/YasinSPC23/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/smacd/YasinSPC23>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/smacd/smacd2023.html#YasinSPC23>
rdfs:seeAlso <https://doi.org/10.1109/SMACD58065.2023.10192137>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/smacd>
dc:title Formal Verification of Divider Circuits by Hardware Reduction. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document