On Achieving Low-Power SoC Clock Tree Synthesis by Transition Time Planning via Buffer Library Study.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/socc/ChenC06
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On Achieving Low-Power SoC Clock Tree Synthesis by Transition Time Planning via Buffer Library Study.
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On Achieving Low-Power SoC Clock Tree Synthesis by Transition Time Planning via Buffer Library Study.
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