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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/socc/FilhoRC16>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jiang_Chau_Wang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jorge_Luis_Gonzalez_Reano>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jose_Eduardo_Chiarelli_Bueno_Filho>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FSOCC.2016.7905431>
foaf:homepage <https://doi.org/10.1109/SOCC.2016.7905431>
dc:identifier DBLP conf/socc/FilhoRC16 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FSOCC.2016.7905431 (xsd:string)
dcterms:issued 2016 (xsd:gYear)
rdfs:label Intra-chip traffic generation under autoregressive models based on time series obtained by TLM simulation. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jiang_Chau_Wang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jorge_Luis_Gonzalez_Reano>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jose_Eduardo_Chiarelli_Bueno_Filho>
swrc:pages 41-46 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/socc/2016>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/socc/FilhoRC16/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/socc/FilhoRC16>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/socc/socc2016.html#FilhoRC16>
rdfs:seeAlso <https://doi.org/10.1109/SOCC.2016.7905431>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/socc>
dc:title Intra-chip traffic generation under autoregressive models based on time series obtained by TLM simulation. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document