Hardware-in-the-loop simulation of a UAV autonomous landing algorithm implemented in SoC FPGA. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Hubert_Szolc>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Tomasz_Kryjak>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.23919%2FSPA53010.2022.9927847>
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dc:identifier	DBLP conf/spa/SzolcK22 (xsd:string)
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dcterms:issued	2022 (xsd:gYear)
rdfs:label	Hardware-in-the-loop simulation of a UAV autonomous landing algorithm implemented in SoC FPGA. (xsd:string)
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rdfs:seeAlso	<http://dblp.uni-trier.de/db/conf/spa/spa2022.html#SzolcK22>
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dc:title	Hardware-in-the-loop simulation of a UAV autonomous landing algorithm implemented in SoC FPGA. (xsd:string)
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