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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/uemcom/HinguFCLYQ23>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chanakya_Hingu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jiang_Lu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Letu_Qingge>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rajab_Challoo>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xiaokun_Yang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xingang_Fu>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FUEMCON59035.2023.10316098>
foaf:homepage <https://doi.org/10.1109/UEMCON59035.2023.10316098>
dc:identifier DBLP conf/uemcom/HinguFCLYQ23 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FUEMCON59035.2023.10316098 (xsd:string)
dcterms:issued 2023 (xsd:gYear)
rdfs:label Accelerating FPGA Implementation of Neural Network Controllers via 32-bit Fixed-Point Design for Real-Time Control. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chanakya_Hingu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jiang_Lu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Letu_Qingge>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rajab_Challoo>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xiaokun_Yang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xingang_Fu>
swrc:pages 445-450 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/uemcom/2023>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/uemcom/HinguFCLYQ23/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/uemcom/HinguFCLYQ23>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/uemcom/uemcom2023.html#HinguFCLYQ23>
rdfs:seeAlso <https://doi.org/10.1109/UEMCON59035.2023.10316098>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/uemcom>
dc:title Accelerating FPGA Implementation of Neural Network Controllers via 32-bit Fixed-Point Design for Real-Time Control. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document