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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vdat/ChoudharyBFS22>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Lava_Bhargava>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Masahiro_Fujita>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Pooja_Choudhary>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Virendra_Singh>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F978-3-031-21514-8%5F36>
foaf:homepage <https://doi.org/10.1007/978-3-031-21514-8_36>
dc:identifier DBLP conf/vdat/ChoudharyBFS22 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F978-3-031-21514-8%5F36 (xsd:string)
dcterms:issued 2022 (xsd:gYear)
rdfs:label Synthesis of LUT Based Approximating Adder Circuits with Formal Error Guarantees. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Lava_Bhargava>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Masahiro_Fujita>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Pooja_Choudhary>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Virendra_Singh>
swrc:pages 435-449 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vdat/2022>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vdat/ChoudharyBFS22/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vdat/ChoudharyBFS22>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vdat/vdat2022.html#ChoudharyBFS22>
rdfs:seeAlso <https://doi.org/10.1007/978-3-031-21514-8_36>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vdat>
dc:title Synthesis of LUT Based Approximating Adder Circuits with Formal Error Guarantees. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document