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dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sisir_Kumar_Jena>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVDAT50263.2020.9190571>
foaf:homepage <https://doi.org/10.1109/VDAT50263.2020.9190571>
dc:identifier DBLP conf/vdat/JenaBD20 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVDAT50263.2020.9190571 (xsd:string)
dcterms:issued 2020 (xsd:gYear)
rdfs:label Approximate Testing of Digital VLSI Circuits using Error Significance based Fault Analysis. (xsd:string)
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swrc:pages 1-6 (xsd:string)
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rdfs:seeAlso <https://doi.org/10.1109/VDAT50263.2020.9190571>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vdat>
dc:title Approximate Testing of Digital VLSI Circuits using Error Significance based Fault Analysis. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
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