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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vdat/MaheshwaramPSBM17>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Anand_Bulusu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mohit_Sharma_0003>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Om._Prakash>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sanjeev_Manhas>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Satish_Maheshwaram>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F978-981-10-7470-7%5F24>
foaf:homepage <https://doi.org/10.1007/978-981-10-7470-7_24>
dc:identifier DBLP conf/vdat/MaheshwaramPSBM17 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F978-981-10-7470-7%5F24 (xsd:string)
dcterms:issued 2017 (xsd:gYear)
rdfs:label Vertical Nanowire FET Based Standard Cell Design Employing Verilog-A Compact Model for Higher Performance. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Anand_Bulusu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mohit_Sharma_0003>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Om._Prakash>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sanjeev_Manhas>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Satish_Maheshwaram>
swrc:pages 239-248 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vdat/2017>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vdat/MaheshwaramPSBM17/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vdat/MaheshwaramPSBM17>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vdat/vdat2017.html#MaheshwaramPSBM17>
rdfs:seeAlso <https://doi.org/10.1007/978-981-10-7470-7_24>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vdat>
dc:title Vertical Nanowire FET Based Standard Cell Design Employing Verilog-A Compact Model for Higher Performance. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document