[RDF data]
Home | Example Publications
PropertyValue
dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vdat/RaveendranKVS19>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Aneesh_Raveendran>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/David_Selvakumar>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Vinay_Kumar>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Vivian_Desalphine>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F978-981-32-9767-8%5F41>
foaf:homepage <https://doi.org/10.1007/978-981-32-9767-8_41>
dc:identifier DBLP conf/vdat/RaveendranKVS19 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F978-981-32-9767-8%5F41 (xsd:string)
dcterms:issued 2019 (xsd:gYear)
rdfs:label Functional Simulation Verification of RISC-V Instruction Set Based High Level Language Modeled FPU. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Aneesh_Raveendran>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/David_Selvakumar>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Vinay_Kumar>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Vivian_Desalphine>
swrc:pages 496-509 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vdat/2019>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vdat/RaveendranKVS19/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vdat/RaveendranKVS19>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vdat/vdat2019.html#RaveendranKVS19>
rdfs:seeAlso <https://doi.org/10.1007/978-981-32-9767-8_41>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vdat>
dc:title Functional Simulation Verification of RISC-V Instruction Set Based High Level Language Modeled FPU. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document