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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsi-dat/ChiouHCHL19>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chang-Chieh_Cheng>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chi-Ray_Huang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jing-Yu_Huang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Lih-Yih_Chiou>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wei-Suo_Ling>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVLSI-DAT.2019.8741606>
foaf:homepage <https://doi.org/10.1109/VLSI-DAT.2019.8741606>
dc:identifier DBLP conf/vlsi-dat/ChiouHCHL19 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVLSI-DAT.2019.8741606 (xsd:string)
dcterms:issued 2019 (xsd:gYear)
rdfs:label A Variation-Tolerant Bitline Leakage Sensing Scheme for Near-Threshold SRAMs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chang-Chieh_Cheng>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chi-Ray_Huang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jing-Yu_Huang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Lih-Yih_Chiou>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wei-Suo_Ling>
swrc:pages 1-4 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsi-dat/2019>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsi-dat/ChiouHCHL19/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsi-dat/ChiouHCHL19>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsi-dat/vlsi-dat2019.html#ChiouHCHL19>
rdfs:seeAlso <https://doi.org/10.1109/VLSI-DAT.2019.8741606>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsi-dat>
dc:title A Variation-Tolerant Bitline Leakage Sensing Scheme for Near-Threshold SRAMs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document