A 6.4 Gb/s source synchronous receiver core with variable offset equalizer in 65nm CMOS.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/vlsi-dat/YuZHXWZW13
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A 6.4 Gb/s source synchronous receiver core with variable offset equalizer in 65nm CMOS.
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