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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsi/AghighiTT20a>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Amin_Aghighi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Armin_Tajalli>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mohammad_Taherzadeh-Sani>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVLSI-SOC46417.2020.9344076>
foaf:homepage <https://doi.org/10.1109/VLSI-SOC46417.2020.9344076>
dc:identifier DBLP conf/vlsi/AghighiTT20a (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVLSI-SOC46417.2020.9344076 (xsd:string)
dcterms:issued 2020 (xsd:gYear)
rdfs:label A Low-Power 10 to 15 Gb/s Common-Gate CTLE Based on Optimized Active Inductors. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Amin_Aghighi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Armin_Tajalli>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mohammad_Taherzadeh-Sani>
swrc:pages 171-175 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsi/2020>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsi/AghighiTT20a/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsi/AghighiTT20a>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2020.html#AghighiTT20a>
rdfs:seeAlso <https://doi.org/10.1109/VLSI-SOC46417.2020.9344076>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsi>
dc:title A Low-Power 10 to 15 Gb/s Common-Gate CTLE Based on Optimized Active Inductors. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document