Asynchronous Integration of Coarse-Grained Reconfigurable XPP-Arrays Into Pipelined Risc Processor Datapath.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/vlsi/BeckerTS03a
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Asynchronous Integration of Coarse-Grained Reconfigurable XPP-Arrays Into Pipelined Risc Processor Datapath.
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Asynchronous Integration of Coarse-Grained Reconfigurable XPP-Arrays Into Pipelined Risc Processor Datapath.
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