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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsi/ChampacRG15>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Alejandra_Nicte-ha_Reyes>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Andres_F._Gomez>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/V%E2%88%9A%E2%89%A0ctor_H._Champac>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVLSI-SoC.2015.7314410>
foaf:homepage <https://doi.org/10.1109/VLSI-SoC.2015.7314410>
dc:identifier DBLP conf/vlsi/ChampacRG15 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVLSI-SoC.2015.7314410 (xsd:string)
dcterms:issued 2015 (xsd:gYear)
rdfs:label Circuit performance optimization for local intra-die process variations using a gate selection metric. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Alejandra_Nicte-ha_Reyes>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Andres_F._Gomez>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/V%E2%88%9A%E2%89%A0ctor_H._Champac>
swrc:pages 165-170 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsi/2015soc>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsi/ChampacRG15/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsi/ChampacRG15>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2015.html#ChampacRG15>
rdfs:seeAlso <https://doi.org/10.1109/VLSI-SoC.2015.7314410>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsi>
dc:title Circuit performance optimization for local intra-die process variations using a gate selection metric. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document